計算系統的基礎設計由處理單元與記憶體之間的關係所定義。主要區別在於指令與資料是否共用同一傳輸路徑，或使用獨立的通道。
1. 馮·諾伊曼架構
一般用途系統（如 x86-64）採用此模型，其特點是統一的記憶體空間。中央處理器透過單一匯流排同時存取程式碼與資料，進而產生 馮·諾伊曼瓶頸：當中央處理器必須在取得指令與存取運算數之間切換匯流排時所產生的延遲。
2. 哈佛架構
常見於特殊用途處理器與 ARMv8-A L1 快取實作中，此設計使用物理上分離的記憶體儲存空間與訊號路徑。這使得操作碼與資料運算數可同時被讀取，顯著提升吞吐量。
流程圖：馮·諾伊曼架構中的記憶體讀取週期，顯示匯流排依序使用的狀況。
3. 結構融合
現代高性能計算系統通常採用 改良型哈佛架構。它們在 L1 快取層級表現得像哈佛機器（指令快取與資料快取分離），以最大化速度，同時在主記憶體層維持馮·諾伊曼模型，以確保程式的彈性。
main.py
TERMINALbash — 80x24
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QUESTION 1
What is the defining characteristic of the von Neumann Bottleneck?
The CPU speed is slower than the bus speed.
A single bus must alternate between fetching code and accessing data.
The memory capacity is too small for modern code.
The L1 cache and L2 cache use different voltages.
✅ Correct!
Correct. Because the bus is shared, instruction fetches and data transfers cannot happen at the exact same moment.❌ Incorrect
The bottleneck refers specifically to the contention on the shared bus between instructions and data.QUESTION 2
Which architecture is typically used for L1 cache implementations in ARMv8-A?
Pure von Neumann
Harvard Architecture
Stack-based Architecture
Single-Bus CISC
✅ Correct!
Correct. ARMv8-A uses a split L1 (Instruction/Data) cache, which follows the Harvard model.❌ Incorrect
ARM and modern processors use split caches (Harvard) at the level closest to the core to maximize throughput.QUESTION 3
In a Modified Harvard Architecture, where does the 'von Neumann' aspect usually reside?
At the L1 Cache level
At the Main RAM/Global Memory level
Inside the Arithmetic Logic Unit
In the register file
✅ Correct!
Correct. Main memory is usually unified (von Neumann) for ease of programming and resource allocation.❌ Incorrect
The split occurs at the cache level; the main memory remains unified to allow data and code to be managed as a single pool.QUESTION 4
What advantage does a von Neumann architecture provide to Just-In-Time (JIT) compilers?
It prevents memory fragmentation.
It treats written instructions exactly like data variables.
It allows for higher clock frequencies.
It automatically encrypts memory.
✅ Correct!
Correct. Since instructions and data share a memory model, code can be written to memory and then executed as an instruction.❌ Incorrect
JIT compilation relies on the ability to write executable code into a data buffer, a core feature of the unified vN model.QUESTION 5
How many clock cycles are minimally required to fetch one instruction and one data operand in a pure Harvard architecture?
One cycle (Simultaneous fetch)
Two cycles (Sequential fetch)
Four cycles (Multiplexed fetch)
Zero cycles (Pre-cached)
✅ Correct!
Correct. Because pathways are separate, the instruction and data can be accessed in the same cycle.❌ Incorrect
The primary benefit of Harvard is parallel access, allowing both fetches to complete in a single cycle.Case Study: Memory Pathway Efficiency
Architectural Analysis of Throughput
A developer is optimizing a high-frequency trading algorithm. On an x86-64 server, the algorithm stalls during data-heavy operations. The developer considers migrating to an ARMv8-A system utilizing separate L1 instruction and data caches.
Q
Based on the text, how does the system distinguish between a code address and a data address in the Harvard architecture?
Solution:
In a Harvard architecture, the system distinguishes between code and data addresses through physical separation. The architecture utilizes separate signal pathways (buses) and dedicated memory storage for instructions and data. Because the hardware uses different physical lines for these requests, the CPU identifies the type of access based on which hardware pathway is being utilized for the transaction.
In a Harvard architecture, the system distinguishes between code and data addresses through physical separation. The architecture utilizes separate signal pathways (buses) and dedicated memory storage for instructions and data. Because the hardware uses different physical lines for these requests, the CPU identifies the type of access based on which hardware pathway is being utilized for the transaction.
Q
Explain how the 'Modified Harvard Architecture' provides a balance between the two paradigms in modern HPC.
Solution:
The Modified Harvard Architecture implements split L1 caches (Instruction and Data) to allow simultaneous fetches at the execution core level, providing the performance benefits of Harvard. However, it maintains a unified main memory and L2/L3 caches, which allows for von Neumann-style flexibility, such as self-modifying code, JIT compilation, and unified memory management.
The Modified Harvard Architecture implements split L1 caches (Instruction and Data) to allow simultaneous fetches at the execution core level, providing the performance benefits of Harvard. However, it maintains a unified main memory and L2/L3 caches, which allows for von Neumann-style flexibility, such as self-modifying code, JIT compilation, and unified memory management.
Q
What icon or label would you place on the bus of a von Neumann flowchart to indicate its primary limitation?
Solution:
A 'Bottleneck' icon or label should be placed on the shared bus. This signifies that the single pathway must handle both instructions and data, causing idle time and stalling the CPU whenever it must switch between these two types of transfers.
A 'Bottleneck' icon or label should be placed on the shared bus. This signifies that the single pathway must handle both instructions and data, causing idle time and stalling the CPU whenever it must switch between these two types of transfers.